Memory device including page buffers

A memory device comprising:

• a memory cell array;
• a plurality of bit lines coupled to the memory cell array and including a plurality of even bit lines and a plurality of odd bit lines, which extend in a first direction and are alternately disposed;
• 2^k number of data lines where k is a natural number equal to or greater than 2, respectively corresponding to 2^k number of input/output pins;
• an even cache latch group including 2^k number of cache latches which are respectively coupled to 2^k number of the even bit lines and are respectively allocated to the input/output pins;
• an odd cache latch group including 2^k number of cache latches which are respectively coupled to 2^k number of the odd bit lines and are respectively allocated to the input/output pins;
• and
• a plurality of column merge units respectively allocated to the input/output pins, and suitable for coupling the 2^k number of cache latches included in the even cache latch group or the 2^k number of cache latches included in the odd cache latch group, to the data lines, in response to column select signals,
• wherein the cache latches of the even cache latch group and the odd cache latch group have a two-dimensional arrangement in the first direction and a second direction intersecting the first direction, and
• wherein a pitch of the column merge units in the second direction is greater than a pitch of the cache latches in the second direction.