High speed level shifter for high voltage applications

A method comprising:

• generating a primary pulsed input in response to an input signal;
• activating a first transistor when the primary pulsed input is at logic high;
• generating a secondary pulsed input in response to the input signal;
• inactivating a second transistor when the secondary pulsed input is at logic low;
• transitioning a first node from a first voltage level to a second voltage level;
• storing the first voltage level and the second voltage level in a latch coupled to the first node and a second node;
• generating a first control signal when the first node transitions from the first voltage level to the second voltage level;
• and
• activating a third transistor by the first control signal to maintain the first node at a fixed voltage level, wherein a source terminal of the third transistor is coupled to a threshold voltage source.

An ultrasound system comprising a transmitter, the transmitter further comprising:

• a level shifter configured to receive an input signal and configured to generate an output signal;
• a driver coupled to the level shifter and configured to generate a drive signal in response to the output signal;
• and
• a main transistor whose gate terminal is coupled to the driver, whose source terminal is coupled to a voltage supply source and whose drain terminal is coupled to a transducer, wherein the level shifter further comprising:
• a first logic block configured to receive an input signal and configured to generate a primary pulsed input;
• a first transistor coupled between the first logic block and a first node, a gate terminal of the first transistor configured to receive the primary pulsed input;
• a latch coupled to the first node and a second node;
• a second logic block configured to receive the input signal and configured to generate a secondary pulsed input;
• a second transistor coupled between the second logic block and the second node, a gate terminal of the second transistor configured to receive the secondary pulsed input;
• a third logic block coupled to the first node and configured to generate a first control signal;
• and
• a third transistor whose gate terminal is configured to receive the first control signal and whose source terminal is coupled to a threshold voltage source, and a drain terminal of the third transistor is coupled to the first node.