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US 10,319,329 B2Granted
Gate driving circuit, level shifter, and display device
AssigneeSilicon Works Co., Ltd.
InventorsHyun Jin Jeon, Jin Soo Byeon, Ji Hun Kim, Young Jin Woo
Life of this patent
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Abstract
The present invention attenuates noise appearing at neighboring electrodes by causing a rising edge of one clock signal to be synchronized with a falling edge of another one clock signal when a clock signal for gate driving is generated.
Claims16
A gate driving circuit comprising:
- a control signal reception unit for receiving a first clock control signal and a second clock control signal from a timing controller;
- a level shifting unit for generating a plurality of clock signals having voltage levels different from those of the first clock control signal and the second clock control signal, each of the plurality of clock signals including at least one voltage rising section, which is formed in synchronization with the first clock control signal, and at least one voltage falling section, which is formed in synchronization with the second clock control signal;
- and
- a gate driving signal supply unit for supplying a gate driving signal generated according to the plurality of clock signals to a plurality of gate lines disposed on a display panel,
- wherein each of the gate lines is coupled to one electrode disposed on the display panel by capacitance, and one voltage rising section of one clock signal of the plurality of clock signals is synchronized with one voltage falling section of another one clock signal,
- wherein a common electrode is disposed on the display panel, and the common electrode and the gate lines are coupled with each other by capacitance.
3 more elements
A level shifter comprising:
- a control signal reception unit for receiving a first clock control signal and a second clock control signal from a timing controller;
- and
- a level shifting unit for generating a plurality of clock signals having voltage levels different from those of the first clock control signal and the second clock control signal, each of the plurality of clock signals including at least one voltage rising section, which is formed in synchronization with the first clock control signal, and at least one voltage falling section, which is formed in synchronization with the second clock control signal,
- wherein a gate driving signal generated according to the plurality of clock signals is supplied to a plurality of gate lines disposed on a display panel,
- each of the gate lines is coupled to one electrode disposed on the display panel by capacitance, and
- one voltage rising section of one clock signal of the plurality of clock signals is synchronized with one voltage falling section of another one clock signal,
- wherein a common electrode is disposed on the display panel, and the common electrode and the gate lines are coupled with each other by capacitance.
4 more elements
A display device comprising:
- a timing controller for transmitting a first clock control signal and a second clock control signal;
- a display panel on which a plurality of gate lines coupled to one electrode by capacitance are arranged;
- and
- a gate driving circuit for generating a plurality of clock signals having voltage levels different from those of the first clock control signal and the second clock control signal, each of the plurality of clock signals including at least one voltage rising section, which is formed in synchronization with the first clock control signal, and at least one voltage falling section, which is formed in synchronization with the second clock control signal, and for supplying a gate driving signal generated according to the plurality of clock signals to the plurality of gate lines,
- wherein one voltage rising section of one clock signal of the plurality of clock signals is synchronized with one voltage falling section of another one clock signal,
- wherein a common electrode is disposed on the display panel, and the common electrode and the gate lines are coupled with each other by capacitance.
3 more elements
Dependencies are inferred from the claim text.