Shift registers, driving methods, gate driving circuits and display apparatuses with reduced shift register output signal voltage switching time

A shift register, comprising:

• an input unit coupled to an input signal terminal, a first voltage terminal and a pull-up point, and configured to couple the first voltage terminal to the pull-up point under a control of an input signal from the input signal terminal;
• a pull-up unit coupled to the pull-up point, a clock signal terminal and an output signal terminal, and configured to couple the clock signal terminal to the output signal terminal under a control of a voltage at the pull-up point;
• a reset unit coupled to a reset signal terminal, a second voltage terminal and the pull-up point, and configured to couple the second voltage terminal to the pull-up point under a control of a reset signal from the reset signal terminal;
• a pull-down control unit coupled to the pull-up point, the second voltage terminal, a third voltage terminal and the pull-down point, and configured to selectively couple one of the second voltage terminal and the third voltage terminal to the pull-down point under a control of the voltage at the pull-up point;
• a pull-down unit coupled to the pull-down point, the second voltage terminal, the pull-up point and the output signal terminal, and configured to couple the second voltage terminal to the pull-up point and the output signal terminal under a control of a voltage at the pull-down point;
• and
• a pull-up holding unit coupled to a pull-up holding signal terminal, a fourth voltage terminal and the pull-up point, and configured to couple the fourth voltage terminal to the pull-up point under a control of a pull-up holding signal from the pull-up holding signal terminal, to maintain the voltage at the pull-up point to be valid,
• wherein the pull-up unit comprises a third transistor, which has a control electrode coupled to the pull-up point, a first electrode coupled to the clock signal terminal and a second electrode coupled to the output signal terminal, and
• wherein the valid voltage maintained at the pull-up point controls the third transistor to be turned on so as to couple the clock signal terminal to the output signal terminal when an invalid signal is being applied to the clock signal terminal, and controls the output signal terminal to output an invalid signal.