GOA circuit and a liquid crystal display

A GOA circuit comprising:

• a pull-up circuit, comprising a first switching transistor;
• a pull-down circuit, comprising a second switching transistor;
• a scanning output terminal coupled to a second connecting terminal of the first switching transistor, and a first connecting terminal of the second switching transistor;
• a clamping circuit, coupling to the second connecting terminal of the first switching transistor and a second connecting terminal of the second switching transistor, and coupling to the control terminal of the first switching transistor and a control terminal of the second switching transistor;
• and
• a downstream circuit comprising a ninth switching transistor with a control terminal coupled to a control terminal of the first switching transistor, a first connecting terminal coupled to a first connecting terminal of the first switching transistor and a second connecting terminal coupled to a stage transmission output terminal;
• when the scanning output terminal outputs a first electric level, controlling an electric level of the control terminal of the second switching transistor to be lower than an electric level of the second connecting terminal of the second switching transistor, and when the scanning output terminal outputs a second electric level, controlling an electric level of the control terminal of the first switching transistor to be lower than an electric level of the second connecting terminal of the first switching transistor, and the first electric level to be higher than the second electric level;
• wherein the clamping circuit comprises:
• a first clamping terminal, inputting a third electric level coupled to the second connecting terminal of the second switching transistor;
• and
• a second clamping terminal, inputting a fourth electric level coupled to the control terminal of the first switching transistor and coupled to the control terminal of the second switching transistor through a control circuit;
• wherein the third electric level is higher than the fourth electric level;
• the control circuit is adapted to control the control terminal of the second switching transistor to receive the fourth electric level of the second clamping terminal when the scanning output terminal outputs the first electric level, and to control the control terminal of the first switching transistor to receive the fourth electric level of the second clamping terminal when the scanning output terminal outputs the second electric level;
• wherein the control circuit comprises:
• a third switching transistor having a control terminal connected to the control terminal of the first switching transistor, a first connecting terminal connected to the control terminal of the second switching transistor and a second connecting terminal connected to the second clamping terminal;
• a fourth switching transistor having a control terminal and a first connecting terminal connected to a third clamping terminal and a second connecting terminal connected to the control terminal of the second switching transistor, wherein a high electric level is inputted to the third clamping terminal;
• a fifth switching transistor having a control terminal connected to the control terminal of the second switching transistor and a second connecting terminal connected to the second clamping terminal;
• and
• a sixth switching transistor having a control terminal connected to the control terminal of the second switching transistor, a first connecting terminal connected to the control terminal of the first switching transistor and a second connecting terminal connected to a first connecting terminal of the fifth switching transistor;
• wherein the control circuit further comprises a first capacitor connected between the first connecting terminal and the second connecting terminal of the sixth switching transistor;
• and
• when the control terminal of the second switching transistor is controlled to receive the fourth electric level of the second clamping terminal, the first capacitor maintains the sixth transistor to be turned off.

A liquid crystal display comprising a GOA circuit, wherein the GOA circuit comprises:

• a pull-up circuit, comprising a first switching transistor;
• a pull-down circuit, comprising a second switching transistor;
• a scanning output terminal coupled to a second connecting terminal of the first switching transistor, and a first connecting terminal of the second switching transistor;
• a clamping circuit, coupling to the second connecting terminal of the first switching transistor and a second connecting terminal of the second switching transistor, and coupling to the control terminal of the first switching transistor and a control terminal of the second switching transistor;
• a downstream circuit comprising a ninth switching transistor with a control terminal coupled to a control terminal of the first switching transistor, a first connecting terminal coupled to a first connecting terminal of the first switching transistor and a second connecting terminal coupled to a stage transmission output terminal;
• and
• a pull-up control circuit, comprising a seventh switching transistor having a control terminal to which is inputted a clock signal and a first connecting terminal to which is inputted a stage transmission signal, and an eighth switching transistor having a control terminal to which is inputted the clock signal and a first connecting terminal coupled to a second connecting terminal of the seventh switching transistor and a second connecting terminal coupled to the control terminal of the first switching transistor;
• the pull-up control circuit further comprises a second capacitor coupled between the first connecting terminal and the second connecting terminal of the eighth switching transistor, and the first connecting terminal of the eighth switching transistor is further coupled to the second connecting terminal of the sixth switching transistor;
• when the scanning output terminal outputs a first electric level, controlling an electric level of the control terminal of the second switching transistor to be lower than an electric level of the second connecting terminal of the second switching transistor, and when the scanning output terminal outputs a second electric level, controlling an electric level of the control terminal of the first switching transistor to be lower than an electric level of the second connecting terminal of the first switching transistor, and the first electric level to be higher than the second electric level;
• wherein the clamping circuit comprises:
• a first clamping terminal, inputting a third electric level coupled to the second connecting terminal of the second switching transistor;
• and
• a second clamping terminal, inputting a fourth electric level coupled to the control terminal of the first switching transistor and coupled to the control terminal of the second switching transistor through a control circuit;
• wherein the third electric level is higher than the fourth electric level;
• the control circuit is adapted to control the control terminal of the second switching transistor to receive the fourth electric level of the second clamping terminal when the scanning output terminal outputs the first electric level, and to control the control terminal of the first switching transistor to receive the fourth electric level of the second clamping terminal when the scanning output terminal outputs the second electric level;
• wherein the control circuit comprises:
• a third switching transistor having a control terminal connected to the control terminal of the first switching transistor, a first connecting terminal connected to the control terminal of the second switching transistor and a second connecting terminal connected to the second clamping terminal;
• a fourth switching transistor having a control terminal and a first connecting terminal connected to a third clamping terminal and a second connecting terminal connected to the control terminal of the second switching transistor, wherein a high electric level is inputted to the third clamping terminal;
• a fifth switching transistor having a control terminal connected to the control terminal of the second switching transistor and a second connecting terminal connected to the second clamping terminal;
• and
• a sixth switching transistor having a control terminal connected to the control terminal of the second switching transistor, a first connecting terminal connected to the control terminal of the first switching transistor and a second connecting terminal connected to a first connecting terminal of the fifth switching transistor;
• wherein the control circuit further comprises a first capacitor connected between the first connecting terminal and the second connecting terminal of the sixth switching transistor;
• and
• when the control terminal of the second switching transistor is controlled to receive the fourth electric level of the second clamping terminal, the first capacitor maintains the sixth transistor to be turned off.