Display device including a shift register including a plurarality of stages connected as a cascade and method of operating the same

A display device, comprising:

• a pixel array comprising:
• data lines and gate lines;
• and
• pixels in a matrix, the pixels being at intersections of the data lines and gate lines;
• a shift register comprising a plurality of stages connected as a cascade, the shift register being configured to sequentially supply respective gate pulses to the gate lines;
• and
• a node controller configured to control nodes in the shift register,
• wherein a first stage among the plurality of stages comprises:
• a pull-up transistor configured to charge the output in response to a voltage on a Q node to output a first gate pulse,
• a pull-down transistor configured to discharge the output to a gate-low voltage in response to a QB node voltage,
• a start controller configured to pre-charge the Q node in response to a start pulse or a gate pulse other than the first gate pulse, and
• a QB node discharge controller configured to discharge the QB node to a first low-potential voltage in response to a voltage at a first reset signal input line,
• wherein the node controller comprises a first reset signal generator including:
• a gate electrode connected to a gate-low voltage input line,
• a drain electrode connected to a high-potential voltage input line, and
• a source electrode connected to the first reset signal input line,
• wherein the first reset signal generator is configured to, during a vertical blanking interval of each frame, charge the first reset signal input line in response to a turn-on voltage applied to the gate-low voltage input line.