Gate driving circuit and display device including the same

A gate driving circuit comprising:

• a shift register including a plurality of stages,
• wherein an nth stage of the plurality of stages includes:
• a latch control circuit including a first NMOS transistor connected to a QB node, a second NMOS transistor connected to a Q node, and a third NMOS transistor having a gate electrode to which a first clock is input and connected to the first NMOS transistor and the second NMOS transistor;
• a latch connected between the Q node and the QB node;
• and
• a buffer including a transmission gate connected to the Q node and the QB node and having a source electrode to which a second clock is input,
• wherein n is a positive integer,
• wherein in the latch control circuit, the first NMOS transistor includes a gate electrode to which a first carry signal from an n−1th stage is input and a drain electrode connected to the QB node, and the second NMOS transistor includes a gate electrode to which a second carry signal from an n+1th stage is input and a drain electrode connected to the Q node, and
• wherein the first carry signal from an n−1th stage is not an inverting signal of the second carry signal from an n+1th stage.