Shift register unit, driving method thereof, gate driving circuit and display device

A shift register unit comprising:

• an input circuit coupled to an input signal terminal, a reset signal terminal, a first control signal terminal, a second control signal terminal, and a pull-up node, the input circuit being configured to control an electric potential of the pull-up node under a control of an input signal from the input signal terminal, a reset signal from the reset signal terminal, a first control signal from the first control signal terminal, and a second control signal from the second control signal terminal;
• an output circuit coupled to a first clock signal terminal, the pull-up node, and an output terminal, the output circuit being configured to transmit a first clock signal from the first clock signal terminal to the output terminal under a control of the pull-up node;
• a pull-down control circuit coupled to a first power supply signal terminal, a second power supply signal terminal, the pull-up node, a pull-down node, and the reset signal terminal, the pull-down control circuit being configured to:
• transmit a first power supply signal from the first power supply signal terminal to the pull-down node under a control of the first power supply signal,
• transmit the first power supply signal from the first power supply signal terminal to the pull-down node under a control of the reset signal, and
• transmit a second power supply signal from the second power supply signal terminal to the pull-down node under a control of the pull-up node,
• wherein the first power supply signal is at a first electric potential, and the second power supply signal is at a second electric potential;
• and
• a pull-down circuit coupled to the pull-down node, the second power supply signal terminal, the pull-up node, and the output terminal, the pull-down circuit being configured to transmit the second power supply signal to the pull-up node and the output terminal under a control of the pull-down node.