Shift register with reduced wiring complexity

An image processor comprising:

• a two-dimensional execution lane array;
• and
• a two-dimensional shift-register array comprising a plurality of rows and columns of shifting unit cells, wherein the shifting unit cells in a particular row or column are physically arranged out of logical order, each shifting unit cell comprising local register space and circuitry having inputs configured to receive shifted data and outputs configured to transmit shifted data, wherein each of the inputs is assigned a different respective shift amount and each of the outputs is assigned a different respective shift amount, wherein the circuitry of each shifting unit cell comprises:
• (i) first circuitry configured to receive data from a preceding logically ordered shifting unit cell at a respective input assigned to a respective shift amount specified in a shift command and to write the received data into the local register space of the shifting unit cell, and
• (ii) second circuitry configured to transmit data to a following logically ordered cell from a respective output assigned to an incremented shift amount from a shift amount of an input at which the data was received.