Multi-microcontroller system, internet of things gateway system, and control flow of multi-microcontroller system based on network bridge

An Internet of Things gateway system, comprising:

• a master microcontroller, a network bridge and a plurality of slave microcontrollers;
• wherein the master microcontroller and the network bridge are arranged in a master device, and the plurality of slave microcontrollers are each arranged in a plurality of electronic devices;
• the network bridge forms a first communication part with a first memory interface and a first SPI interface;
• the master microcontroller is connected with the first communication part through a second communication part, and the second communication part comprises a second memory interface and a second SPI interface;
• the plurality of slave microcontrollers are connected with the first communication part through a third communication part, and the third communication part comprises a third memory interface and a third SPI interface;
• thus the plurality of electronic devices are managed by the master device via the network bridge;
• wherein the network bridge is connected with the second communication part and the third communication part respectively via the first communication part, processes transmission of control signals and data between the master microcontroller and the plurality of slave microcontrollers, and serves as a temporary storage area for common memory such that the states of the plurality of slave microcontrollers are put under automated management, the addresses of the plurality of slave microcontrollers are designated, and memory blocks are allocated.

A control flow of a multi-microcontroller system based on a network bridge, the multi-microcontroller system comprising a master microcontroller and a plurality of slave microcontrollers, wherein the master microcontroller is connected with the plurality of slave microcontrollers respectively via a network bridge, the control flow comprises the following steps:

• step 1:
• initializing the master microcontroller, the network bridge and the plurality of slave microcontrollers;
• step 2:
• inquiring the master microcontroller and the plurality of slave microcontrollers and assigning IDs and addresses to the master microcontroller and the plurality of slave microcontrollers by the network bridge;
• step 3:
• returning the number of the plurality of slave microcontrollers to the master microcontroller and then judging whether the master microcontroller sends a command of data retrieval by the network bridge;
• if so, proceeding with step 4, and if not, returning to step 1;
• step 4:
• analyzing the command sent by the master microcontroller by the network bridge, wherein the command includes a designated ID of one of the plurality of slave microcontrollers and a control command;
• step 5:
• executing the control command on the designated ID of the slave microcontroller;
• and
• step 6:
• receiving a value returned by the slave microcontroller, and returning to step 1 upon the completion of reception;
• wherein a memory interface functions as a data communication interface and an SPI interface functions as a state control interface among the master microcontroller, the network bridge and the slave microcontroller.