Packet processing method and apparatus

A method, comprising:

• receiving, by a first network device, a packet that is from a second network device, wherein the packet carries a first time, and the first time is a time at which the second network device receives the packet;
• processing, by the first network device, the packet to obtain a processed packet, and writing the processed packet into a buffer memory;
• reading, by the first network device, the processed packet from the buffer memory at a second time;
• determining, by the first network device at a time after the second time, a first latency of the processed packet in a first in first out (FIFO) memory, wherein the first latency is equal to a difference obtained by subtracting a second latency from a target latency, the target latency is equal to a period from the first time to a third time at which the processed packet is forwarded by the first network device through an egress port, the second latency is equal to a sum of a third latency and a fourth latency, the third latency is equal to a period from the first time to the second time, the fourth latency is a fixed latency, and the FIFO memory comprises multiple contiguous storage units;
• setting, by the first network device, a read pointer and/or a write pointer according to the determined first latency;
• writing, by the first network device according to the set write pointer, the processed packet into a storage unit in the FIFO memory, or reading, according to the set read pointer, the processed packet from a storage unit in the FIFO memory;
• and
• forwarding, by the first network device at the third time through the egress port, the processed packet that is read from the FIFO memory.

An apparatus, comprising:

• a receiver, configured to receive a packet at a first time;
• a processor;
• and
• a computer-readable storage medium storing a program to be executed by the processor, the program including instructions for:
• processing the packet to obtain a processed packet, and write the processed packet into a buffer memory;
• reading, from the buffer memory at a second time, the processed packet;
• determining, at a time after the second time, a first latency of the processed packet in a first in first out (FIFO) memory, wherein the first latency is equal to a difference obtained by subtracting a second latency from a target latency, the target latency is equal to a period from the first time to a third time at which the processed packet is forwarded through an egress port, the second latency is equal to a sum of a third latency and a fourth latency, the third latency is equal to a period from the first time to the second time, the fourth latency is a fixed latency, and the FIFO memory comprises multiple contiguous storage units;
• setting a read pointer and/or a write pointer according to the first latency;
• writing, according to the set write pointer, the processed packet into a storage unit in the FIFO memory, or read, according to the set read pointer, the processed packet from a storage unit in the FIFO memory;
• and
• forwarding, at the third time through the egress port, the processed packet that is read from the FIFO memory.

An apparatus, comprising:

• a receiver, configured to receive a packet that is from a second network device, wherein the packet carries a first time, and the first time is a time at which the second network device receives the packet;
• a processor;
• and
• a computer-readable storage medium storing a program to be executed by the processor, the program including instructions for:
• processing the packet to obtain a processed packet, and writing the processed packet into a buffer memory;
• reading, from the buffer memory at a second time, the processed packet;
• determining, at a time after the second time, a first latency of the processed packet in a first in first out (FIFO) memory, wherein the first latency is equal to a difference obtained by subtracting a second latency from a target latency, the target latency is equal to a period from the first time to a third time at which the processed packet is forwarded through an egress port, the second latency is equal to a sum of a third latency and a fourth latency, the third latency is equal to a period from the first time to the second time, the fourth latency is a fixed latency, and the FIFO memory comprises multiple contiguous storage units;
• setting a read pointer and/or a write pointer according to the first latency;
• writing, according to the set write pointer, the processed packet into a storage unit in the FIFO memory, or reading, according to the set read pointer, the processed packet from a storage unit in the FIFO memory;
• and
• forwarding, at the third time through the egress port, the processed packet that is read from the FIFO memory.