Keyed-hash message authentication code processors, methods, systems, and instructions
AssigneeIntel Corporation
InventorsVinodh Gopal, Jason W. Brandt
Life of this patent
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AssigneeIntel Corporation
InventorsVinodh Gopal, Jason W. Brandt
Estimating the term…
A processor of an aspect includes a decode unit to decode a keyed-hash message authentication code instruction. The keyed-hash message authentication code instruction is to indicate a message, to indicate at least one value that is to represent at least one of key information and key indication information, and to indicate a destination storage location. An execution unit is coupled with the decode unit. The execution unit, in response to the keyed-hash message authentication code instruction, is to store a message authentication code corresponding to the message in the destination storage location. The message authentication code is to be consistent with a keyed-hash message authentication code algorithm that is to use a cryptographic hash algorithm. The message authentication code is to be based on a cryptographic key associated with the at least one value. Other processors, methods, systems, and instructions are disclosed.
A processor comprising:
A method in a general-purpose processor comprising:
A system to process instructions comprising:
An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing instructions including a keyed-hash message authentication code (MAC) with obfuscated key information instruction of an instruction set of a processor, the keyed-hash MAC with obfuscated key information instruction being at least one of a macroinstruction and a machine code instruction,
Dependencies are inferred from the claim text.