Key protecting method and apparatus

A key protection device, comprising a processor and a non-transitory storage, wherein the non-transitory storage is configured to store one or more instructions to be executed by the processor, and the one or more instructions comprise a setting instruction and an operation instruction;

• wherein
• the setting instruction is to execute step A of setting a symmetric master key in each core of the multi-core processor;
• the operation instruction is to execute step B of taking any core of the multi-core processor configured with the symmetric master key as an operation core, performing a decryption operation by the operation core to obtain a plaintext private key using the symmetric master key, performing an asymmetric cryptographic operation by the operation core using the plaintext private key;
• the plaintext private key and intermediate variables used in the asymmetric cryptographic operation being stored in a cache occupied by the operation core and further execute step C of clearing up the plaintext private key and the intermediate variables in the cache occupied by the operation core,
• wherein the setting instruction is further to prohibit OS process scheduling and disable local interrupts before the operation instruction executes the step B and enable the OS process scheduling and the local interrupt after the operation instruction finishes execution of step C;
• and
• wherein the setting instruction is to prohibit the OS process scheduling and disable the local interrupts via clearing up an Interrupt Flag (IF) bit of an EFLAGS register of the multi-core processor and enable the OS process scheduling and local interrupt via setting the IF bit of the EFLAGS register of the multi-core processor.