Energy-efficient bitcoin mining hardware accelerators

An application specific integrated circuit (ASIC) comprising:

• a plurality of registers;
• and
• a plurality of circuits to perform stage-1 secure hash algorithm (SHA) hash and stage-2 SHA hash, wherein to perform the stage-2 SHA hash based on an input message, the ASIC is to:
• perform a plurality of rounds of compression on state data stored in a plurality of registers associated with a stage-2 SHA hash circuit using an input value, wherein the input value comprises a hash value generated by a stage-1 SHA hash circuit, and wherein each register of the plurality of registers is to store a state that is updated through the plurality of rounds of compression;
• calculate a plurality of speculative computation bits using a plurality of bits of the state data;
• and
• transmit the plurality of speculative computation bits to a processor communicatively coupled to the ASIC.

A method comprising:

• transmitting, by a processor, an input message to a hardware accelerator, the input message comprising a target value and a nonce, wherein the hardware accelerator implements a plurality of circuits to perform stage-1 secure hash algorithm (SHA) hash and stage-2 SHA hash;
• instructing the hardware accelerator to perform a plurality of rounds of compression on state data stored in a plurality of registers associated with a stage-2 SHA hash circuit using an input value, wherein the input value comprises a hash value generated by a stage-1 SHA hash circuit, and wherein each register of the plurality of registers is to store a state that is updated through the plurality of rounds of compression;
• instructing the hardware accelerator to calculate a plurality of speculative computation bits using a plurality of bits of the state data;
• and
• receiving, from the hardware accelerator, the plurality of speculative computation bits.