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US 10,313,058 B2Granted
False positive detection using combining gain
AssigneeIntel IP Corporation
InventorsGwang-Hyun Gho, Joan Anton Olivella
Life of this patent
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Abstract
A method for detecting that a set of bits has been incorrectly decoded includes calculating a combining gain experienced during processing of the set of bits. The combining gain is compared to a threshold. A false positive signal that indicates that the set of bits has been incorrectly decoded is generated when the combining gain is less than the threshold.
Claims23
False positive detection circuitry configured to detect a set of bits that has been incorrectly decoded by a user device, comprising:
- a gain circuitry configured to calculate a combining gain experienced during a processing operation performed on the set of bits, wherein the combining gain corresponds to an increase in magnitude of bits in the set of bits that results from the processing operation;
- and
- a decision circuitry configured to:
- compare the combining gain to a threshold;
- generate a false positive signal, which indicates that the set of bits has been incorrectly decoded when the combining gain is less than the threshold;
- and
- wherein in response to the false positive signal, the user device refrains from operating based on the set of bits.
4 more elements
A method for detecting that a set of bits has been incorrectly decoded, comprising:
- calculating a combining gain experienced during a processing operation on the set of bits, wherein the combining gain corresponds to an increase in magnitude of bits in the set of bits that results from the processing operation;
- and
- generating a false positive signal that indicates that the set of bits has been incorrectly decoded based at least on the combining gain;
- and
- in response to the false positive signal, refraining from operating a device based on the set of bits.
2 more elements
A device, comprising:
- a demodulator circuity configured to demodulate a received signal to generate a demodulated set of bits;
- a de-rate match circuitry configured to generate a de-rate-matched set of bits by analyzing redundant bits in the set of bits;
- and
- a false positive detector circuitry configured to detect that the set of bits has been incorrectly decoded based at least on a magnitude of bits in the demodulated set of bits as compared to a magnitude of bits in the de-rate matched set of bits;
- and
- wherein in response to the false positive signal, the device refrains from operating based on the set of bits.
3 more elements
Dependencies are inferred from the claim text.