US 10,313,053 B2 · Enhanced automatic identification system

Abstract

The invention relates to method and apparatus for improving the performance of communication systems using Run Length Limited (RLL) messages such as the existing Automatic Identification System (AIS). A binary data sequence is Forward Error Correction (FEC) coded and then the sequence is compensated, for example by bit-erasure, so that either bit-stuffing is not required, or a bit stuffer will not be activated to ensure that the coded sequence meets the RLL requirement. Various embodiments are described to handle different architectures or input points for the FEC encoder and bit erasure module. The bit erasure module may also add dummy bits to ensure a RLL compliant CRC or to selectively add bits to a reserve buffer to compensate for later bit stuffing in a header. Additional RLL training sequences may also be added to assist in, receiver acquisition.

Claims17

Dependent claims

A method for generating a message for transmission in a system that requires the message to be run length limited (RLL) to a run of n first binary states by bit-stuffing, the method comprising:

coding at least a data portion of a binary sequence for transmission using a forward error correction (FEC) code to generate a FEC coded portion of the binary sequence;
bit erasing one or more bits in at least the FEC coded portion to compensate for the run of n first binary states in the FEC coded portion of the binary sequence so that the FEC coded portion is RLL without requiring insertion of additional bits, wherein the bit-erasing step implements selective bit erasing, wherein if a n+1th bit after the run of n first binary states is equal to a first binary state of the n first binary states, the nth bit is set to a second binary state of the n first binary states and if the n+1th bit after the run of n first binary states is equal to the second binary state, then the n+1th bit is removed from the binary sequence;
bit stuffing the bit erased binary sequence, wherein bit-stuffing comprises insertion of the second binary state after the nth first binary state;
and
providing the bit erased and bit stuffed binary sequence to a transmitter for modulation and subsequent transmission.

2 more elements

An Automatic Identification System (AIS) compliant transmitter, the transmitter comprising:

an encoder configured to encode at least a data portion of a binary sequence for transmission using a forward error correction (FEC) code to generate a FEC coded portion of the binary sequence;
a bit eraser module configured to selectively bit erase one or more bits in at least the FEC coded portion to compensate for a run of n first binary states in the FEC coded portion of the binary sequence so that the FEC coded portion is Run Length Limited (RLL) without requiring insertion of additional bits, wherein the bit eraser module detects a run of n first binary states and then checks the n+1th bit and if equal to the first binary state then the nth bit is set to a second binary state and if the n+1th bit is equal to the second binary state then the n+1th bit is removed from the binary sequence;
a bit stuffing module configured to detect the presence of a run of n bits each with the first binary state and on detection insert a bit with the second binary state after the nth bit;
an interleaver;
and
a modulator configured to modulate an interleaved binary sequence for transmission.

3 more elements

A communication system including:

a transmitter apparatus comprising:
an encoder configured to encode at least a data portion of a binary sequence for transmission using a forward error correction (FEC) code to generate a FEC coded portion of the binary sequence;
a bit eraser module configured to selectively bit erase one or more bits in at least the FEC coded portion to compensate for a run of n first binary states in the FEC coded portion of the binary sequence so that the FEC coded portion is Run Length Limited (RLL) without requiring insertion of additional bits, wherein if a n+1th bit after the run of n first binary states is equal to the first binary state, the nth bit is set to a second binary state and if the n+1th bit after the run of n first binary states is equal to the second binary state, then the n+1th bit is removed from the binary sequence;
and
an interleaver;
and
a modulator configured to modulate an interleaved binary sequence for transmission;
and
a receiver apparatus comprising:
a soft demodulator;
an interleaver module;
and
a soft decoder comprising an FEC decoder module.

10 more elements

Dependencies are inferred from the claim text.

Enhanced automatic identification system

Life of this patent

Enhanced automatic identification system

Life of this patent

Abstract

Claims17