Parallel bit interleaver

A transmitter for transmitting a codeword generated based on a low-density parity check coding scheme, the parity-check matrix of the low-density parity check coding scheme having a quasi-cyclic structure, the parity bits of the codeword being interleaved, the transmitter comprising:

• a bit group permutator that, in operation, applies a bit group permutation process to a codeword made up of N bit groups each consisting of Q bits, to reorder the bit groups in accordance with a bit group permutation rule defining a reordering of the bit groups;
• a bit permutator that, in operation, applies a bit permutation process to the codeword after the bit group permutation process, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits;
• a divider that, in operation, divides the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits;
• a modulator that, in operation, maps each of the constellation words to a modulated signal;
• and
• a transmitter that, in operation, transmits a transmitting signal generated from the modulated signal, wherein
• N is a multiple of M,
• the bit permutation rule defines the reordering of the bits of the codeword after the bit group permutation process, the reordering of the bit permutation rule being equivalent to a column-row permutation process including a writing process and a reading process, the bits of the N bit groups being written into a matrix row-by-row during the writing process, the written bits being read out from the matrix column-by-column during the reading process, the matrix having M rows, the Q bits included in one bit group being written into a same row sequentially, and
• the bit index of the bit in each of the constellation words to which the bits in each of the bit groups are allocated is determined in accordance with the bit group permutation rule.