Noise-shaping analog-to-digital converter
AssigneeAnalog Devices Global Unlimited Company
InventorRoberto Sergio Matteo Maurino
Life of this patent
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Abstract
Shortening any of the operational phases of a noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC), including the acquisition phase, the bit trial phase, and the residue charge transfer phase, can result in higher power, and it can be difficult to achieve high speed at low power. Using various techniques described, the acquisition, bit-trial, and residue charge transfer phases of two or more digital-to-analog converter (DAC) circuits of an ADC circuit can be time-interleaved. The use of two or more DAC circuits can increase or maximize the time available for the acquisition, bit-trial, and residue charge transfer phases.
Claims20
A method of operating a noise-shaping successive approximation register analog-to-digital converter (ADC) circuit including time-interleaved signal acquisition with a shared noise-shaping circuit, the method comprising:
- receiving at a first rate, using a first digital-to-analog converter (DAC) circuit, a first sample of an input signal during an acquisition phase of the first DAC circuit;
- receiving at the first rate, using a second DAC circuit, a second sample of the input signal during an acquisition phase of the second DAC circuit that occurs after the acquisition phase of the first DAC circuit;
- combining a residue charge of the first DAC circuit and a residue charge of the second DAC circuit;
- updating the noise-shaping circuit at a second rate less than the first rate;
- generating an output using the combination of residue charge;
- and
- controlling a timing between the first and second DAC circuits and the noise-shaping circuit to time-interleave acquisition, bit-trial, and residue charge transfer phases of the first and second DAC circuits.
A noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) circuit including time-interleaved signal acquisition with a shared noise-shaping circuit, the ADC circuit comprising:
- a first digital-to-analog converter (DAC) circuit configured to receive, at a first rate, a first sample of an input signal during an acquisition phase of the first DAC circuit;
- a second DAC circuit configured to receive, at the first rate, a second sample of the input signal during an acquisition phase of the second DAC circuit that occurs after the acquisition phase of the first DAC circuit;
- a control circuit configured to:
- control a timing between the first and second DAC circuits and the noise-shaping circuit to time-interleave acquisition, bit-trial, and residue charge transfer phases of the first and second DAC circuits;
- and
- update the noise-shaping circuit at a second rate less than the first rate;
- and
- the noise-shaping circuit configured to:
- combine a residue charge of the first DAC circuit and a residue charge of the second DAC circuit;
- and
- generate an output using the combination of residue charge.
A noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) circuit including time-interleaved signal acquisition with a shared noise-shaping circuit, the ADC circuit comprising:
- means for receiving at a first rate a first sample of an input signal during an acquisition phase of a first digital-to-analog converter (DAC) circuit;
- means for receiving at the first rate a second sample of the input signal during an acquisition phase of a second DAC circuit that occurs after the acquisition phase of the first DAC circuit;
- means for combining a residue charge of the first DAC circuit and a residue charge of the second DAC circuit;
- means for updating the noise-shaping circuit at a second rate less than the first rate;
- means for generating an output using the combination of residue charge;
- and
- means for controlling a timing between the first and second DAC circuits and the noise-shaping circuit to time-interleave acquisition, bit-trial, and residue charge transfer phases of the first and second DAC circuits.
Dependencies are inferred from the claim text.