Dynamic decode circuit with active glitch control method

A method for precharging a plurality of dynamic decode circuits, each dynamic decode circuit of the plurality of dynamic decode circuits comprising a respective plurality of precharge circuits, a respective decoder connected to a respective first node and a respective evaluate circuit, the respective evaluate circuit comprising a first transistor serially connected to a second transistor by way of an interconnecting node, the respective evaluate circuit connected between a second node and a first power source, the each dynamic decode circuit performing the method comprising:

• receiving input signals, by a plurality of inputs of the respective decoder;
• based on the plurality of inputs of the decoder being in a predetermined input state and based on being in an evaluation phase, causing, by the decoder, the first node to be low;
• receiving an evaluation clock signal by a first gate of the first transistor of the respective evaluate circuit;
• receiving the first node by a second gate of the second transistor of the respective evaluate circuit;
• based on the respective first node being low and based on being in the evaluation phase, causing, by the respective evaluate circuit, the second node to be high;
• precharging the respective first node to a high state, by a first precharge circuit of the respective plurality of precharge circuits, comprising a first precharge transistor, based on not being in the evaluation phase of the evaluation clock signal;
• precharging the second node to the high state, by a second precharge circuit, by a first precharge circuit of the respective plurality of precharge circuits, comprising a second precharge transistor, based on not being in the evaluation phase of the evaluation clock signal;
• and
• precharging the interconnecting node of the respective evaluate circuit to the high state, by a third precharge circuit of the respective plurality of precharge circuits, comprising a third precharge transistor, based on not being in the evaluation phase of the evaluation clock signal.