Gate control for a tristate output buffer
AssigneeTexas Instruments Incorporated
InventorChristopher Michael Graves
Life of this patent
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Abstract
A gate control circuit for a tristate output buffer operating in a first voltage domain includes a pull-up circuit coupled between an upper rail and a first gate control signal, a pull-down circuit coupled between a lower rail and a second gate control signal, and a gate isolation switch coupled between the first gate control signal and the second gate control signal. The gate isolation switch includes a first PMOS transistor coupled in parallel with a first NMOS transistor. The first NMOS transistor is controlled by a first enable signal and the first PMOS transistor is controlled by a second enable signal.
Claims6
A gate control circuit comprising:
- a pull-up circuit coupled between an upper rail and a first gate control signal output;
- a pull-down circuit coupled between a lower rail and a second gate control signal output;
- and
- a gate isolation switch including a first PMOS transistor coupled in parallel with a first NMOS transistor between the first gate control signal output and the second gate control signal output, the first NMOS transistor being controlled by a first enable signal and the first PMOS transistor being controlled by a second enable signal.
A voltage translator comprising:
- an input buffer having an input signal input, a first input control signal output and a second input control signal output, the input buffer operating in a first voltage domain;
- a level shifter having inputs coupled to the first and second input control signal outputs and having an output control signal output;
- a gate control circuit having inputs coupled to the first and second input control signal outputs and to the output control signal output and having a first gate control signal output and a second gate control signal output;
- and
- an output buffer having inputs coupled to the first gate control signal output, the second gate control signal output, and an output signal output, the level shifter, the gate control circuit and the output buffer operating in a second voltage domain, the gate control circuit including:
- a pull-up circuit coupled between an upper rail and the first gate control signal output;
- a pull-down circuit coupled between a lower rail and a the second gate control signal output;
- and
- a gate isolation switch including a first PMOS transistor and a second PMOS transistor coupled in parallel with a first NMOS transistor and a second NMOS transistor between the first gate control signal output and the second gate control signal output, the first and second NMOS transistors being controlled by a first enable signal and the first and second PMOS transistor being controlled by a second enable signal, the first PMOS transistor and the first NMOS transistor having a first threshold voltage, the second PMOS transistor and the second NMOS transistor having a second threshold voltage that is lower than the first threshold voltage.
Dependencies are inferred from the claim text.