US 10,312,893 B2Granted

Apparatuses and methods for adjusting timing of signals

AssigneeMicron Technology, Inc.

InventorYantao Ma

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Abstract

Apparatuses and methods for adjusting timing of signals are described herein. An example apparatus may include a first signal adjustment cell configured to receive a first clock signal and to adjust skew of rising or falling edges of the first clock signal based on a first control signal. The timing adjustment circuit may further include a second signal adjustment cell configured to adjust skew of rising or falling edges of a second clock signal based on a second control signal. The timing adjustment circuit may further include a differential adjustment cell configured to receive the first and second clock signals and to adjust skew of rising or falling edges of the first clock signal based on the first control signal and to adjust skew of rising or falling edges of the second clock signal based on the second control signal. The first and second clock signals may be complementary.

Claims19

Dependent claims

An apparatus comprising a clock adjusting circuit, wherein the clock adjusting circuit is configured to receive an input clock signal and provide an adjusted clock signal, and wherein the clock adjusting circuit comprises:

an input terminal configured to receive the input clock signal;
an output terminal configured to provide the adjusted clock signal;
a first bias terminal configured to receive a first bias signal;
a first inverter including a first input node and a first output node, the first input node being coupled to the input terminal, wherein the first inverter is configured to operate with a drive strength that is substantially constant;
and
a second inverter including a second input node, a second output node and a first bias node, the second input node being coupled to the first output node of the first inverter, the second output node being coupled to the first input node of the first inverter, the first bias node being couple to the first bias terminal, and the second inverter being configured to serve as a bias controlled inverter to operate with a drive strength that is based, at least in part, on the first bias signal.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/604,297Filed 24 May 2017 · continuation
Priority: 3 Dec 2014
Published: US 2017/0264277 A114 Sep 2017
Granted: 4 Jun 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03K 5/12
Shaping pulses: by steepening leading or trailing edges
H03K 5/05
By increasing duration; by decreasing duration: by the use of clock signals or other time reference signals
H03K 5/1565
Arrangements in which a continuous pulse train is transformed into a train having a desired pattern: the output pulses having a constant duty cycle
H03K 5/134
Using a chain of active delay devices: with field-effect transistors

Family

Application62/087,123Us provisional application · filed 3 Dec 2014
Application14/806,551Parent of this continuation · filed 22 Jul 2015
US 2017/0264277 A1Pre-grant publication · published 14 Sep 2017
US 9,698,766 B2Parent of this continuation
US 2016/0164509 A1Published application
US 10,312,893 B2This patent

From the US filing history. Foreign family members aren’t listed.

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