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US 10,312,888 B2Granted
Systems and methods for a robust double node upset tolerant latch
AssigneeBoard of Trustees of Southern Illinois University on Behalf of Southern Illinois University Carbondale
InventorsAdam Watkins, Spyros Tragoudas
Life of this patent
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Abstract
Various embodiments of a robust double node upset tolerant latch in which all internal and external nodes are capable of recovering the previous value after a single event upset are disclosed.
Claims20
A double node upset (DNU) tolerant latch circuit comprising:
- a first storage circuit (C1) and a second storage circuit (C2), each comprising three inputs and an output;
- a third storage circuit (C3) and a fourth storage circuit (C4), each comprising two inputs and an output;
- wherein the output of the first storage circuit (C1) is electrically connected to an input of the second storage circuit (C2);
- the output of the second storage circuit (C2) is electrically connected to the fourth storage circuit (C4);
- the output of the third storage circuit (C3) is electrically connected to an input of the second storage circuit (C2);
- and the output of the fourth storage circuit (C4) is electrically connected to an input of the first storage circuit (C1) and an input of the third storage circuit (C3).
3 more elements
A method for preventing double node upsets (DNUs) in a latch circuit, the method comprising:
- electrically interconnecting:
- a first storage circuit (C1) and a second storage circuit (C2), each comprising three inputs and an output;
- and
- a third storage circuit (C3) and a fourth storage circuit (C4), each comprising two inputs and an output;
- wherein the output of the first storage circuit (C1) is electrically connected to an input of the second storage circuit (C2);
- the output of the second storage circuit (C2) is electrically connected to the fourth storage circuit (C4);
- the output of the third storage circuit (C3) is electrically connected to an input of the second storage circuit (C2);
- and the output of the fourth storage circuit (C4) is electrically connected to an input of the first storage circuit (C1) and an input of the third storage circuit (C3).
5 more elements
Dependencies are inferred from the claim text.