Systems and methods of active clamp flyback power converters

A method of operation a power converter, comprising:

• activating a main switch of a primary circuit of an active-clamp flyback power converter, and thereby inducing a positive current flow in a primary winding of a transformer, the positive current flow resulting in reverse biasing of an active or passive rectifier of a secondary circuit;
• deactivating the main switch and thereby forward biasing the rectifier in the secondary circuit and causing current flow in a secondary winding of the secondary circuit;
• activating a clamp electrically controlled switch of the primary circuit, and thereby coupling a clamp capacitor to a leakage inductance of the transformer, the primary circuit having initially a positive current flow through the primary winding and then a negative current flow through the primary winding;
• and
• regulating the negative current flow through the primary winding by:
• deactivating the clamp FET;
• activating a timer responsive to deactivating the clamp FET;
• monitoring a signal indicative of negative current flow through the primary winding;
• and if the signal indicative of negative current flow does not fall below a predetermined threshold prior to expiration of the timer
• activating the main FET;
• and
• making a non-linear change of frequency of an oscillator providing a clock signal.

A semiconductor device for controlling an active clamp flyback power converter, the semiconductor device comprising:

• a substrate of semiconductor material;
• an oscillator defined on the substrate, the oscillator has a clock output and a modulate input, the oscillator configured to generate a clock signal at a clock frequency on the clock output based on a modulate signal received on the modulate input;
• a voltage sense circuit defined on the substrate, the voltage sense circuit has a sense input and a sense output, the sense input configured to couple to a signal indicative of current flow through a primary winding of a transformer of the power converter, and the voltage sense circuit configured to generate a sense signal on the sense output;
• a modulation circuit defined on the substrate, the modulation circuit has a clock input, a sense input, and a modulate output, the clock input coupled to the clock signal, the sense input coupled to the sense signal, and the modulate output coupled to the modulate input of the oscillator;
• a clamp control circuit defined on the substrate, the clamp control circuit has a clock input, a sense input, and a clamp drive output, the clock input of the clamp control circuit coupled to the clock signal, the sense input of the clamp control circuit coupled to the sense signal, and the clamp drive output configured to couple to a gate of a clamp field effect transistor (FET) of the power converter;
• a main control circuit defined on the substrate, the main control circuit has a sense input, a feedback input, and a main drive output, the sense input of the main control circuit coupled to the sense signal, the feedback input configured to couple to a feedback signal from a secondary side of the power converter, and the main drive output configured to couple to a gate of a main FET of the power converter;
• the main control circuit is configured to assert the main drive output responsive to the sense signal falling through a first predetermined threshold, and the main control circuit further configured to de-assert the main drive output based on the feedback signal;
• the clamp control circuit is configured to assert the clamp drive output responsive to the sense signal rising through a second predetermined threshold after the main drive output is de-asserted, and the clamp control circuit further configured to de-assert the clamp drive output responsive to assertion of the clock signal;
• and
• the modulation circuit is configured to monitor the sense signal, and configured to regulate the clock frequency of the clock signal by changing the modulate signal driven to the modulate output based on the sense signal.

An active clamp flyback power converter comprising:

• a primary circuit comprising:
• a primary winding of a flyback transformer having a first terminal coupled to an input node, and a second terminal defining a switch node;
• a main field effect transistor (FET) coupled between the switch node and a ground or common of the primary circuit;
• a clamp FET in series with a clamp capacitor, the clamp FET and clamp capacitor coupled between the input node and the switch node;
• a secondary circuit comprising:
• a secondary winding of the flyback transformer;
• and
• a rectifier coupled between a terminal of the secondary winding and ground or common of the secondary circuit;
• a controller defining a main drive output coupled to a gate of the main FET, a clamp drive output coupled to a gate of the clamp FET, and a current sense input coupled to the primary circuit;
• the controller is configured to:
• activate the main FET and thereby induce a positive current flow in the primary winding, the positive current flow resulting in reverse biasing of the rectifier of the secondary circuit;
• deactivate the main FET and thereby forward bias the rectifier in the secondary circuit and cause current flow in the secondary winding;
• activate the clamp FET and thereby couple the clamp capacitor to a leakage inductance of the flyback transformer, the primary circuit having initially a positive current flow through the primary winding and then a negative current flow through the primary winding;
• and
• regulate the negative current flow through the primary winding by changing a frequency of an oscillator providing a clock signal to de-activate the clamp FET, the changing responsive to a signal indicative of negative current flow during periods of time when both the main FET and the clamp FET are deactivated.