Monolithic integration of high voltage transistors and low voltage non-planar transistors

An integrated circuit (IC) structure, comprising:

• a plurality of non-planar bodies, each comprising semiconductor;
• a first field effect transistor (FET) over a first region of a substrate layer, wherein the FET includes:
• a first and a second of the non-planar bodies the first and second bodies extending from well portions of the substrate layer that comprise an impurity dopant;
• a first channel region between the first and second bodies, and between the well portions;
• a first source region and a second source region in the first of the non-planar bodies;
• a first drain region and a second drain region in the second of the non-planar bodies;
• and
• a first gate stack over the first channel region;
• and
• a second FET over a second region of the substrate layer, wherein the second FET includes:
• a third of the non-planar bodies;
• a third source region in the third of the non-planar bodies;
• a third drain region in the third of the non-planar bodies;
• a second channel region in the third of the non-planar bodies, the second channel region between the third source region and the third drain region;
• and
• a second gate stack over the second channel region.