Semiconductor device with contamination improvement

A semiconductor device, comprising:

• a substrate;
• two gate structures disposed on the substrate and separated from each other, wherein:
• two doped regions are respectively disposed at two opposite sides of each of the gate structures,
• the doped regions disposed at two opposite sides of a first gate structure of the gate structures are equal in size to the doped regions disposed at two opposite sides of a second gate structure of the gate structures, and
• a top surface of an isolation structure between a first doped region of the doped regions disposed at two opposite sides of the first gate structure and a second doped region of the doped regions disposed at two opposite sides of the second gate structure is not higher than the first doped region and is not higher than the second doped region;
• an etching stop layer covering the substrate and the doped regions, and peripherally surrounding the gate structures;
• an interlayer dielectric layer disposed on the etching stop layer, wherein a top of the interlayer dielectric layer has at least one concave surface;
• and
• a material layer disposed on the at least one concave surface of the interlayer dielectric layer, wherein:
• a material forming the material layer is metal,
• at a smallest distance between the material layer and the first gate structure, the material layer is separated from the first gate structure by the etching stop layer and a spacer disposed between the first gate structure and the etching stop layer,
• the material layer has a top surface which is elevated at the same level with top surfaces of the gate structures, and
• a ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures substantially ranges from 1/30 to 1/80.

A semiconductor device, comprising:

• a substrate;
• two gate structures disposed on the substrate, wherein:
• the gate structures are separated by an isolation structure which is disposed in the substrate,
• two doped regions are respectively disposed at two opposite sides of each of the gate structures, and
• the doped regions disposed at two opposite sides of one of the gate structures are equal in size to the doped regions disposed at two opposite sides of another one of the gate structures;
• two spacers peripherally surrounding the gate structures respectively, wherein the spacers have a tapered sidewall;
• an etching stop layer covering the substrate, the isolation structure, the doped regions, and the spacers;
• an interlayer dielectric layer disposed on the etching stop layer and peripherally surrounding the gate structures;
• and
• a material layer disposed on the interlayer dielectric layer, wherein:
• a material forming the material layer is metal,
• at a smallest distance between the material layer and a first gate structure of the gate structures, the material layer is separated from the first gate structure by the etching stop layer and a first spacer of the spacers peripherally surrounding the first gate structure,
• the material layer has a top surface which is elevated at the same level with top surfaces of the gate structures, and
• a ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures substantially ranges from 1/30 to 1/80.