Laterally diffused MOSFET on fully depleted SOI having low on-resistance
AssigneeAvago Technologies International Sales Pte. Limited
InventorsQing Liu, Akira Ito, Shom Surendran Ponoth
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AssigneeAvago Technologies International Sales Pte. Limited
InventorsQing Liu, Akira Ito, Shom Surendran Ponoth
Estimating the term…
Laterally diffused MOSFETs on fully depleted SOI are provided. A laterally diffused MOSFET includes a substrate and a first semiconductor layer disposed on the substrate. The laterally diffused MOSFET also includes a buried oxide layer disposed on the first semiconductor layer. A second semiconductor layer that comprises a first gate region, a drain region, and a source region is disposed on the buried oxide layer. The first gate region is positioned between the source and drain regions. A first shallow trench isolation is disposed between the drain region and the first semiconductor layer. A second gate region is disposed on the first semiconductor layer away from the second semiconductor layer and between the first shallow trench isolation and a second shallow trench isolation. A gate node is coupled to the first and second gate regions to apply a gate voltage to the first and second gate regions.
A semiconductor device, comprising:
A method of creating a laterally diffused MOSFET, comprising:
A method of operating a laterally diffused n-type MOSFET, the laterally diffused n-type MOSFET including a first gate region, a second gate region, a source region, and a drain region, the method comprising:
Dependencies are inferred from the claim text.