Trenched vertical power field-effect transistors with improved on-resistance and breakdown voltage

A method of fabricating a vertical transistor, comprising:

• depositing a semiconductor structure including a first III-nitride layer on a second III-nitride layer and comprising a lateral channel, wherein:
• a polar c-plane interface and nonpolar and/or semipolar interfaces are between the first III-nitride layer and the second III-nitride layer;
• the lateral channel is connected to a drift region;
• the drift region comprising one or more doped Gallium Nitride layers;
• depositing a source contact to the lateral channel;
• depositing a drain contact to the drift region;
• depositing one or more gates on the lateral channel and positioned to modulate current flowing vertically from the source contact, through the drift region, and to the drain contact;
• and
• forming a trench region around a current carrying region of the drift region;
• and wherein:
• the polar interface is between the drift region and one or more gates,
• the trench region comprises a current blocking structure comprising different material layers that can provide a compensating charge,
• the compensating charge can fully deplete an ionized dopant concentration in a current carrying region of the drift region in an off-state,
• modulation of a current from a source to a drain occurs in the lateral channel,
• voltage is predominantly held in a vertical direction in the off-state, and
• the current is channeled through an aperture in the current-blocking structure after it flows from under the gates into the drift region in an on-state.