Method for producing trench high electron mobility devices

A method for producing a transistor device, comprising:

• a) on a silicon substrate having a substantially flat topside and a substantially flat, oppositely disposed bottomside, forming a first dielectric layer over an epitaxial layer at least partially covering the topside;
• b) depositing a photoresist material over the first dielectric layer;
• c) removing a predetermined portion of the photoresist material to define a negative photoresist pattern;
• d) removing a predetermined portion of the first dielectric layer corresponding to the negative photoresist pattern to define an exposed portion;
• e) implanting dopants into the exposed portion to define a doped portion;
• f) removing silicon from a second exposed portion to generate trenches having V-shaped cross-sections and having first and second angled sidewalls intersecting to define the V-shaped cross-section, wherein each angled sidewall defining the V-shaped cross-section is a silicon face having a 111 orientation and wherein the first dielectric is removed before removing silicon from the second exposed portion;
• g) removing remaining first dielectric layer;
• hi) applying a growth promoter to the at least one sidewall;
• h2) after hi), applying a stress buffer layer to the at least one sidewall;
• h3) after h2), forming a first GaN layer on the at least one sidewall;
• h4) after h3), forming an Al0.27Ga0.73N layer over the first GaN layer;
• h5) after h4), forming a second GaN layer over the Al0.27Ga0.73N layer to yield a 2DEG layer;
• i) depositing a third dielectric layer over the at least one sidewall;
• j) forming a first buffer layer in electric communication with the bottomside;
• k) forming at least one ohmic contact in the first buffer layer to define a Drain;
• l) depositing a second dielectric layer to fill in trenches and planarize the silicon substrate;
• m) doping the first buffer layer to define a highly doped buffer layer;
• n) applying gate oxides to predetermined portions of the topside to define Gate regions;
• o) applying a first metallization layer over predetermined portions of the topside to define source regions;
• p) applying a passivation layer over the first metallization layer;
• r) activating the respective dopants;
• s) applying a second metallization layer over the bottomside;
• and t) after s), annealing the substrate;
• wherein the doped portion has a dopant concentration of between about 1013 dopants per cubic centimeter and about 1018 dopants per cubic centimeter;
• wherein the highly doped buffer layer has a dopant concentration of between about 1018 dopants per cubic centimeter and about 1020 dopants per cubic centimeter;
• wherein the highly doped buffer layer is between about 1 micron thick and about 3 microns thick;
• wherein the passivation layer is between about 0.4 micron thick and about 0.8 microns thick;
• wherein the first dielectric layer is between about 1 Angstrom unit thick and about 10 microns thick;
• and wherein the first dielectric material is selected from the group including SiO2, Si3N4, and combinations thereof;
• wherein the first buffer layer is formed before forming the first dielectric layer and prior to forming the epitaxial layer.