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US 10,312,359 B2Granted
Guard rings for cascode gallium nitride devices
AssigneeSemiconductor Components Industries, LLC
InventorsWoochul Jeon, Chun-Li Liu, Ali Salih
Life of this patent
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Abstract
Implementations of semiconductor devices may include: a plurality of drain fingers and a plurality of source fingers interdigitated with one another; at least one gate; and at gate bus formed to completely surround the plurality of drain fingers and the plurality of source fingers; wherein the gate bus is mechanically and electrically coupled to the at least one gate.
Claims20
A semiconductor device comprising:
- a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gates;
- an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads;
- and
- a gate bus formed as a guard ring of the D-mode transistor;
- wherein the gate bus is coupled with one or more gate pads of the D-mode transistor;
- and
- wherein the one or more gate pads of the D-mode transistor couple with the source pads of the E-mode transistor and an electrical ground.
4 more elements
A semiconductor device comprising:
- a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gates;
- an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads;
- and
- a gate bus formed as a guard ring of the D-mode transistor;
- wherein the gate bus is coupled with one or more gate pads of the D-mode transistor;
- and
- wherein the one or more gate pads of the D-mode transistor couple with the source pads of the E-mode transistor and an electrical ground;
- and
- wherein the source is not grounded.
6 more elements
A semiconductor device comprising:
- a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gates;
- an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads;
- and
- a gate bus formed as a guard ring of the D-mode transistor;
- a second guard ring surrounding an outer perimeter of the first guard ring;
- wherein the gate bus is coupled with one or more gate pads of the D-mode transistor;
- and
- wherein the one or more gate pads of the D-mode transistor couple with the source pads of the E-mode transistor and an electrical ground.
5 more elements
Dependencies are inferred from the claim text.