Tunnel field-effect transistor (TFET) with lateral oxidation
AssigneeBoard of Regents, The University of Texas System
InventorsJack C. Lee, Han Zhao
Life of this patent
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Abstract
A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.
Claims23
A tunnel field-effect transistor (TFET), comprising:
- a substrate;
- a source region;
- a drain region having a first dimension;
- a channel region coupled to the drain region;
- a tunnel region coupled to the source region and the drain region;
- and
- an oxide region, having a second dimension, wherein:
- the oxide region is positioned laterally relative to the source region, wherein:
- the source region, the drain region, and the channel region are vertically stacked over the substrate, and
- the first dimension of the drain region is equal to the second dimension of the oxide region.
A tunnel field-effect transistor (TFET), comprising:
- a substrate;
- a source region;
- a drain region;
- a channel region coupled to the drain region;
- a tunnel region having a first portion coupled to the channel region;
- an oxide region positioned at least partially under the drain region, the channel region, and the first portion of the tunnel region;
- and
- a gate region that overlaps with at least a portion of the channel region and at least a second portion of the tunnel region, wherein:
- the drain region, the channel region, the tunnel region, and the source region are made from a first material, and
- the substrate is made from a second material different from the first material.
A tunnel field-effect transistor (TFET), comprising:
- a first layer having a first portion and a second portion, wherein the first portion of the first layer includes a source region, and wherein the second portion of the first layer includes an oxide region having a first width;
- a second layer that includes a tunnel region, wherein the tunnel region includes a first portion having a second width;
- a third layer that includes a channel region;
- and
- a fourth layer that includes a drain region, wherein:
- the first width is less than or equal to the second width, and
- the oxide region, by virtue of the first width, restricts a path of an OFF-state leakage current that flows in the TFET.
Dependencies are inferred from the claim text.