Vertical transistor with variable gate length

A method of forming a vertical transistor, the method comprising of:

• patterning a hardmask layer on a semiconductor substrate;
• transferring the patterned hardmask layer into the semiconductor substrate, wherein transferring comprises etching a plurality of trenches into the semiconductor substrate to define a plurality of fins at a constant pattern density, the plurality of fins comprising dummy fins;
• forming a bottom spacer layer without having to remove the patterned hardmask layer, wherein the bottom spacer layer has a uniform thickness between the plurality of fins, wherein the bottom spacer layer comprises silicon nitride (SiN);
• forming an oxide layer on the bottom spacer layer to a top surface of the patterned hardmask layer on the plurality of fins;
• removing the dummy fins and forming a plurality of deep trenches into the semiconductor substrate at locations of the dummy fins, wherein removing the dummy fins provides the plurality of fins with a variable pattern density;
• and
• depositing a dielectric material to a top surface of the patterned hardmask layer on the plurality of fins and etching the dielectric material to a top surface of the bottom space layer and form isolation regions of the dielectric material in each of the plurality of deep trenches.