Memory transistor with multiple charge storing layers and a high work function gate electrode

A semiconductor device, comprising:

• a memory transistor formed over a substrate, the memory transistor including:
• a gate structure;
• a channel positioned between and electrically connecting a first diffusion region formed in the substrate and a second diffusion region formed above the substrate, wherein the channel is vertical and formed in a cylinder of semiconducting material oriented substantially perpendicular to a surface of the substrate;
• and
• a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel, wherein the multi-layer charge trapping layer comprises a first dielectric layer disposed abutting the tunnel dielectric layer, an anti-tunneling layer abutting the first dielectric layer, and a second dielectric layer abutting the anti-tunneling layer, and wherein the first and the second dielectric layers include a nitride, and the anti-tunneling layer is thinner than the first and second dielectric layers and comprises a stoichiometric composition substantially free of nitride;
• and
• a metal oxide semiconductor (MOS) logic device formed at least partially over the surface of the substrate, MOS logic device including a gate oxide layer and a gate electrode disposed thereon.

A semiconductor device, comprising:

• a memory transistor including:
• a gate structure including a high work function gate electrode comprising a doped polysilicon layer;
• a channel positioned between and electrically connecting a first diffusion region and a second diffusion region;
• and
• a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel, wherein the multi-layer charge trapping layer comprises a first dielectric layer disposed abutting the tunnel dielectric layer, an anti-tunneling layer abutting the first dielectric layer, and a second dielectric layer abutting the anti-tunneling layer, and wherein the anti-tunneling layer comprises a stoichiometric composition adapted to reduce a probability of electron charge in the second nitride layer from tunneling into the first nitride layer during programming of the memory transistor;
• and
• a metal oxide semiconductor (MOS) logic device including a gate oxide layer and a gate electrode disposed thereon.