Gate with self-aligned ledge for enhancement mode GaN transistors

An enhancement-mode GaN transistor, comprising:

• a GaN layer;
• a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer;
• a source contact and a drain contact formed on the barrier layer;
• a p-type gate material formed above the barrier layer, the p-type gate material having side surfaces extending horizontally towards the source contact and drain contact, respectively, and contacting the barrier layer;
• and
• a gate metal disposed on the p-type gate material, the gate metal having sidewalls extending towards the p-type gate material,
• wherein the p-type gate material comprises a pair of horizontal ledges that extend past the respective sidewalls of the gate metal and toward the source contact and the drain contact, respectively, the pair of horizontal ledges having substantially equal widths from the sidewalls of the gate metal to the side surfaces of the p-type gate material, respectively.