Power semiconductor device

A power semiconductor device, comprising:

• a base substrate;
• a first epitaxial layer disposed on the base substrate;
• a second epitaxial layer disposed on the first epitaxial layer;
• an anode electrode and a cathode electrode disposed on the second epitaxial layer;
• a p-type well region disposed below the anode electrode inside the second epitaxial layer;
• an NISO region disposed below the p-type well region, and in which at least a portion is located inside the first epitaxial layer;
• and
• an n-type buried layer disposed below the NISO region, and in which at least a portion is located inside the base substrate.

A power semiconductor device, comprising:

• a substrate including:
• a first epitaxial layer,
• a second epitaxial layer, and
• a base substrate, the first epitaxial layer being disposed between the second epitaxial layer and the base substrate;
• and
• a plurality of unit cells disposed on the substrate, each of the plurality of unit cells including:
• an anode electrode and a cathode electrode disposed at a distance away from each other on the substrate,
• a well region disposed inside the substrate below the anode electrode, and having a p-type conductivity, and
• an NISO region disposed below the well region, and having a first n-type impurity concentration inside the substrate;
• and
• an n-type buried layer disposed below the NISO region of each of the plurality of unit cells, and having a second n-type impurity concentration greater than the first n-type impurity concentration inside the substrate.