Semiconductor memory device

A semiconductor memory device comprising:

• a substrate;
• a plurality of first wirings arranged in a first direction crossing a surface of the substrate;
• a second wiring extending in the first direction;
• a variable resistance film provided between the first wiring and the second wiring;
• a third wiring extending in a second direction crossing the first direction;
• a select transistor provided between an end of the second wiring and the third wiring;
• and
• a chalcogen layer provided at at least one of a position between the end of the second wiring and the select transistor, and, a position between the third wiring and the select transistor, wherein
• the select transistor comprises:
• a semiconductor layer being connected to the second wiring or the third wiring, and including:
• a first semiconductor region;
• and
• a second semiconductor region between the first semiconductor region and the chalcogen layer;
• and
• a gate electrode facing the second semiconductor region, and
• the chalcogen layer is connected to the second semiconductor region.

A semiconductor memory device comprising:

• a substrate;
• a plurality of first wirings arranged in a first direction crossing a surface of the substrate;
• a second wiring extending in the first direction;
• a variable resistance film provided between the first wiring and the second wiring;
• a third wiring extending in a second direction crossing the first direction;
• a select transistor connected to the third wiring;
• and
• a chalcogen layer connected to the select transistor and the second wiring, wherein
• the select transistor comprises:
• a semiconductor layer including one end connected to the third wiring, and, the other end connected to the chalcogen layer;
• and
• a gate electrode facing the semiconductor layer in the second direction.