Transistor with self-aligned source and drain contacts and method of making same

A method, comprising:

• forming a gate structure that includes a first sidewall and a second sidewall;
• forming a first vertical dielectric spacer on the first sidewall and a second vertical dielectric spacer on the second sidewall;
• forming a source region adjacent the gate structure with at least part of the first vertical dielectric spacer located between the source region and the gate structure;
• forming a drain region adjacent the gate structure with at least part of the second vertical dielectric spacer located between the source region and the gate structure;
• providing a sacrificial layer over the source region and the drain region, the sacrificial layer having a top surface that is substantially coplanar with a top surface of the gate structure and the first and second vertical dielectric spacers;
• forming a gate structure block mask that extends over the gate structure and the first and second vertical dielectric spacers;
• forming a source/drain mask on the dummy layer over the source region and the drain region adjacent the gate structure block mask;
• while forming the source/drain mask, exposing a third sidewall and a fourth sidewall of the gate structure, wherein the third and fourth sidewalls are not parallel to nor aligned with the first and second sidewalls of the gate structure;
• forming a third vertical dielectric spacer on any exposed sidewalls of the source region, on any exposed sidewalls of the drain region, on any exposed sidewalls of the source/drain mask, on any exposed sidewalls of the gate structure block mask, on the third sidewall of the gate structure, and on the fourth sidewall of the gate structure;
• selectively removing the source/drain mask and the sacrificial layer to form openings over the source and drain regions that are delimited by the first, second and third vertical dielectric spacers;
• and
• filling said openings with a conductive material to form source and drain contact structures.

A method, comprising:

• forming an intermediate transistor structure including:
• an active region supported by a substrate and including a source region, a channel region and a drain region;
• and
• a gate stack over the channel region;
• forming a first sidewall spacer on sidewalls of the gate stack;
• epitaxially growing a raised source region and a raised drain region over the source and drain regions, respectively, of the active region and adjacent the first sidewall spacer;
• depositing a sacrificial layer over the raised source region and raised drain region to form a source stack and a drain stack, respectively;
• forming a second sidewall spacer on further sidewalls of the gate stack and which peripherally surrounds the source stack and drain stack;
• selectively removing the sacrificial layer to form openings above the raised source region and raised drain region that are each delimited by the first and second sidewall spacers;
• and
• filling said openings with conductive material to form a source contact and a drain contact to the raised source region and raised drain region, respectively.

A method, comprising:

• forming an intermediate transistor structure including:
• an active region supported by a substrate and including a source region, a channel region and a drain region;
• and
• a gate stack over the channel region;
• forming a first sidewall spacer on first sidewalls of the gate stack;
• forming a raised source region and a raised drain region over the source and drain regions, respectively, of the active region and adjacent the first sidewall spacer;
• depositing a sacrificial layer over the raised source region and raised drain region;
• forming a first mask over the gate stack;
• forming a second mask over the sacrificial layer and the raised source region and raised drain region;
• etching using the first and second masks to define a source stack and drain stack covered by said second mask and expose second sidewalls of the gate stack;
• forming a second sidewall spacer on the second sidewalls and which surrounds the source stack and drain stack;
• removing the second mask;
• etching using the first mask to remove the sacrificial layer and form openings above the raised source region and raised drain region which are delimited by the first and second sidewall spacers;
• and
• filling said openings with conductive material to form a source contact and a drain contact to the raised source region and raised drain region, respectively.