Method of manufacturing three-dimensional stacked semiconductor structure and structure manufactured by the same

A three-dimensional (3D) stacked semiconductor structure, comprising:

• a substrate, having an array area and a peripheral area;
• patterned multi-layered stacks formed in the array area and above the substrate, and the patterned multi-layered stacks spaced apart from each other, and channel holes formed between the patterned multi-layered stacks disposed adjacently;
• a charge trapping layer formed on the patterned multi-layered stacks and deposited in the channel holes as liners;
• a polysilicon channel layer deposited along the charge trapping layer;
• and
• conductive pads formed on the polysilicon channel layer and respectively formed above corresponding one of the patterned multi-layered stacks,
• wherein one of the patterned multi-layered stacks comprises a plurality of insulating layers and a plurality of conductive layers arranged alternately,
• wherein the plurality of conductive layers of one of the patterned multi-layered stacks has a first width (W1), one of the conductive pads has a second width (W2), and the second width (W2) is larger than the first width (W1),
• wherein the polysilicon channel layer has a first thickness (t1), one of the conductive pads has a second thickness (t2), and the second thickness (t2) is larger than the first thickness (t1).