US 10,312,254 B2Granted

Semiconductor device and a manufacturing method thereof

AssigneeRenesas Electronics Corporation

InventorsAtsushi Yoshitomi, Yoshiyuki Kawashima

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Abstract

The reliability and performances of a semiconductor device having a nonvolatile memory are improved. A control gate electrode is formed over a semiconductor substrate via a first insulation film. A memory gate electrode is formed over the semiconductor substrate via a second insulation film having a charge accumulation part. The second insulation film is formed across between the semiconductor substrate and the memory gate electrode, and between the control gate electrode and the memory gate electrode. Between the control gate electrode and the memory gate electrode, a third insulation film is formed between the second insulation film and the memory gate electrode. The third insulation film is not formed under the memory gate electrode. A part of the memory gate electrode is present under the lower end face of the third insulation film.

Claims20

Dependent claims

A semiconductor device, comprising:

a semiconductor substrate;
a first gate electrode for a memory cell of a nonvolatile memory formed over the semiconductor substrate via a first gate insulation film;
a second gate electrode for the memory cell of the nonvolatile memory formed over the semiconductor substrate via a second gate insulation film having a charge accumulation part;
and
a first insulation film formed between the first gate electrode and the second gate electrode,
wherein the second gate insulation film is formed across between the semiconductor substrate and the second gate electrode, and between the first gate electrode and the second gate electrode,
wherein the first insulation film is formed between the second gate insulation film and the second gate electrode, in between the first gate electrode and the second gate electrode, and is in contact with the second gate electrode,
wherein the first gate electrode and the second gate electrode are adjacent to each other via the second gate insulation film and the first insulation film,
wherein the first insulation film is not formed under the second gate electrode,
wherein the lower end face of the first insulation film is at a higher position than that of the lower surface of the second gate electrode, and
wherein a part of the second gate electrode is directly under the lower end face of the first insulation film.

8 more elements

A method for manufacturing a semiconductor device having a memory cell of a nonvolatile memory, the method comprising the steps of:

(a) providing a semiconductor substrate;
(b) forming a first gate electrode for the memory cell over the semiconductor substrate via a first gate insulation film;
(c) forming a second gate insulation film having a charge accumulation part over the semiconductor substrate in such a manner as to cover the first gate electrode;
(d) forming a first insulation film over the second gate insulation film;
(e) forming a second insulation film formed of a different material from that for the first insulation film over the first insulation film;
(f) anisotropically etching the second insulation film, thereby to expose the first insulation film, and to leave the second insulation film over a side surface of the first gate electrode via the second gate insulation film and the first insulation film;
(g) after the step (f), isotropically etching the first insulation film, thereby to expose the second gate insulation film, and to leave the first insulation film and the second insulation film over a side surface of the first gate electrode via the second gate insulation film;
(h) after the step (f), forming a first film for forming a second gate electrode for the memory cell over the second gate insulation film;
and
(i) etching back the first film, thereby to form the second gate electrode,
wherein the second gate electrode is formed over the semiconductor substrate via the second gate insulation film,
wherein the first gate electrode and the second gate electrode are adjacent to each other via the second gate insulation film, the first insulation film, and the second insulation film,
wherein the first insulation film and the second insulation film are not formed under the second gate electrode,
wherein a first lower end face of the first insulation film, and a second lower end face of the second insulation film present between the first gate electrode and the second gate electrode are at a higher position than that of the lower surface of the second gate electrode, and
wherein a part of the second gate electrode is present under the first lower end face of the first insulation film, and the second lower end face of the second insulation film present between the first gate electrode and the second gate electrode.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/699,756Filed 8 Sep 2017
Priority: JP 2016-17762512 Sep 2016
Published: US 2018/0076206 A115 Mar 2018
Granted: 4 Jun 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND
H10D 30/0413
Of FETs having insulated gates [IGFET]: of FETs having charge-trapping gate insulators, e.g. MNOS transistors
H10D 30/60
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]
H10D 30/69
Insulated-gate field-effect transistors [IGFET]: iGFETs having charge trapping gate insulators, e.g. MNOS transistors

Family

US 2018/0076206 A1Pre-grant publication · published 15 Mar 2018
US 10,312,254 B2This patent

From the US filing history. Foreign family members aren’t listed.

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