Split-gate flash memory cell with improved scaling using enhanced lateral control gate to floating gate coupling

An array of non-volatile memory cells, comprising:

• a substrate of semiconductor material of a first conductivity type;
• spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
• each of the active regions including pairs of memory cells, each of the memory cell pairs including:
• a first region and a pair of second regions spaced apart in the substrate having a second conductivity type different from the first conductivity type, with channel regions in the substrate between the first region and the second regions,
• a pair of electrically conductive floating gates each having a first portion disposed vertically over and insulated from a first portion of a respective one of the channel regions, and a second portion disposed vertically over and insulated from the first region, wherein each floating gate of the pair of floating gates includes a sloping upper surface that terminates with a pair of sharp edges at opposing sides of the sloping upper surface of the floating gate,
• a pair of electrically conductive erase gates, each erase gate of the pair of erase gates disposed vertically over and insulated from a respective floating gate of the pair of floating gates, wherein the pair of sharp edges of each floating gate of the pair of floating gates face a respective erase gate of the pair of erase gates, wherein each erase gate of the pair of erase gates has a bottom surface with a portion facing, and having a shape matching that of, the sloping upper surface of the respective floating gate, and wherein the bottom surface of each erase gate of the pair of erase gates further includes a pair of portions, each portion of the pair of portions wraps around a respective sharp edge of the pair of sharp edges of the respective floating gate,
• an electrically conductive control gate having a first portion disposed laterally adjacent to and insulated from the pair of floating gates, and vertically over and insulated from the first region, and
• a pair of electrically conductive select gates each having a first portion disposed vertically over and insulated from a second portion of a respective one of the channel regions, and laterally adjacent to and insulated from a respective floating gate of the pair of floating gates;
• wherein each of the erase gates is formed as part of a conductive erase gate line that extends across the active regions and the isolation regions in a second direction perpendicular to the first direction, and wherein each of the erase gate lines intercepts one of the erase gates in each of the active regions.

A method of forming a nonvolatile memory cell, comprising:

• providing a substrate of semiconductor material of a first conductivity type;
• forming first and second spaced-apart regions in the substrate of a second conductivity type different from the first conductivity type, with a channel region in the substrate therebetween;
• forming an electrically conductive floating gate having a first portion disposed vertically over and insulated from a first portion of the channel region, and a second portion disposed vertically over and insulated from the first region, wherein the floating gate includes a sloping upper surface that terminates with a pair of sharp edges at opposing sides of the sloping upper surface of the floating gate;
• forming an electrically conductive erase gate disposed vertically over and insulated from the floating gate, wherein the pair of sharp edges face and are insulated from the erase gate, wherein the erase gate has a bottom surface with a portion facing, and having a shape matching that of, the sloping upper surface of the floating gate, and wherein the bottom surface of the erase gate further includes a pair of portions, each portion of the pair of portions wraps around a respective sharp edge of the pair of sharp edges;
• forming an electrically conductive control gate having a first portion disposed laterally adjacent to and insulated from the floating gate, and vertically over and insulated from the first region;
• and
• forming an electrically conductive select gate having a first portion disposed vertically over and insulated from a second portion of the channel region, and laterally adjacent to and insulated from the floating gate.

A method of forming an array of non-volatile memory cells, comprising:

• providing a substrate of semiconductor material of a first conductivity type;
• forming spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
• forming pairs of memory cells in each of the active regions, each of the pairs of memory cells is formed by:
• forming a first region and a pair of second regions spaced apart in the substrate having a second conductivity type different from the first conductivity type, with channel regions in the substrate between the first region and the second regions,
• forming a pair of electrically conductive floating gates each having a first portion disposed vertically over and insulated from a first portion of a respective one of the channel regions, and a second portion disposed vertically over and insulated from the first region, wherein each floating gate of the of floating gates includes a sloping upper surface that terminates with a pair of sharp edges at opposing sides of the sloping upper surface of the floating gate,
• forming a pair of electrically conductive erase gates, each erase gate of the pair of erase gates disposed vertically over and insulated from a respective floating gate of the pair of floating gates, wherein the pair of sharp edges of each floating gate of the pair of floating gates face a respective erase gate of the pair of erase gates, wherein each erase gate of the pair of the erase gates has a bottom surface with a portion facing, and having a shape matching that of, the sloping upper surface of the respective floating gate, and wherein the bottom surface of each erase gate of the pair of erase gates further includes a pair of portions, each portion of the pair of portions wraps around a respective sharp edge of the pair of sharp edges of the respective floating gate,
• forming an electrically conductive control gate having a first portion disposed laterally adjacent to and insulated from the pair of floating gates, and vertically over and insulated from the first region, and
• forming a pair of electrically conductive select gates each having a first portion disposed vertically over and insulated from a second portion of a respective one of the channel regions, and laterally adjacent to and insulated from a respective floating gate of the pair of floating gates;
• wherein each of the erase gates is formed as part of a conductive erase gate line that extends across the active regions and the isolation regions in a second direction perpendicular to the first direction, and wherein each of the erase gate lines intercepts one of the erase gates in each of the active regions.