Bi-stable static random access memory (SRAM) bit cells that facilitate direct writing for storage

A static random access memory (SRAM) data array, comprising a plurality of bi-stable SRAM bit cells organized into a plurality of SRAM bit cell rows and a plurality of SRAM bit cell columns, wherein each bi-stable SRAM bit cell of the plurality of bi-stable SRAM bit cells corresponds to an SRAM bit cell row and an SRAM bit cell column, and comprises:

• a substrate;
• a well region formed in the substrate;
• a source region formed adjacent to the well region, wherein a first bipolar junction transistor (BJT) is formed that comprises a base corresponding to the well region, a collector corresponding to the substrate, and an emitter corresponding to the source region;
• a drain region formed adjacent to the well region a distance from the source region, wherein a second BJT is formed that comprises a base corresponding to the well region, a collector corresponding to the substrate, and an emitter corresponding to the drain region;
• a gate region formed over the well region between the source region and the drain region;
• a base tap region formed adjacent to the well region;
• a collector tap region formed adjacent to the substrate;
• a first shallow trench isolation (STI) region formed in the substrate adjacent to a first side of the well region and the source region, wherein a bottom surface of the first STI region is lower in the substrate than a bottom surface of the well region;
• a second STI region formed in the substrate between the base tap region and the collector tap region and adjacent to a second side of the well region and the drain region, wherein a bottom surface of the second STI region is lower in the substrate than the bottom surface of the well region;
• and
• a third STI region formed in the substrate between the drain region and the base tap region, wherein a bottom surface of the third STI region is higher in the well region than the bottom surface of the well region.

A method for manufacturing a bi-stable static random access memory (SRAM) bit cell, comprising:

• forming a first shallow trench isolation (STI) region, a second STI region, and a third STI region, wherein a bottom surface of the first STI region and a bottom surface of the second STI region is lower in a substrate than a bottom surface of the third STI region;
• doping the substrate to form a well region such that a bottom surface of the well region is higher in the substrate than the bottom surfaces of the first STI region and the second STI region, and lower in the substrate than the bottom surface of the third STI region;
• forming a gate region over the well region between the first STI region and the third STI region;
• forming a source region adjacent to the well region between the first STI region and the gate region, wherein a first bipolar junction transistor (BJT) is formed that comprises a base corresponding to the well region, a collector corresponding to the substrate, and an emitter corresponding to the source region;
• forming a drain region adjacent to the well region between the third STI region and the gate region, wherein a second BJT is formed that comprises a base corresponding to the well region, a collector corresponding to the substrate, and an emitter corresponding to the drain region;
• forming a base tap region adjacent to the well region between the second STI region and the third STI region;
• and
• forming a collector tap region adjacent to the substrate adjacent to the second STI region.