Integrated memory and integrated assemblies

Integrated memory, comprising:

• a pair of neighboring capacitors;
• one of the neighboring capacitors being a first capacitor having a first storage, and the other of the neighboring capacitors being a second capacitor having a second storage node;
• the first and second storage nodes together having a configuration, along a cross-section, of an outer pair of sidewalls and an inner pair of sidewalls;
• the inner pair of sidewalls having upper surfaces which are recessed relative to upper surfaces of the outer pair of sidewalls;
• the first and second storage nodes having upper regions along the upper surfaces of the outer pair of sidewalls, having lower regions beneath the upper regions, and having middle regions between the upper regions and the lower regions;
• an upper-level lattice along the upper regions of the first and second storage nodes and on outer peripheries of the outer pair of sidewalls;
• a middle-level lattice along the middle regions of the first and second storage nodes and between the inner pair of sidewalls;
• a first transistor coupled with the first storage node;
• and
• a second transistor coupled with the second storage node.