US 10,312,240 B2 · Memory cell

Abstract

A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.

Claims25

Dependent claims

A microelectronic component comprising:

A memory cell that includes:
an insulating layer;
a semiconductor layer overlying the insulating layer and including a doped source region, a doped drain region, and an intermediate region between the drain region and the source region;
an insulated front gate electrode overlying the intermediate region;
a first back gate electrode arranged under the insulating layer, opposite the drain region;
and
a second back gate electrode arranged under the insulating layer, opposite the source region;
and
a semiconductor substrate, wherein the insulating layer overlies the semiconductor substrate, the first back gate electrode including a first doped region of the semiconductor substrate and being of a first conductivity type, and the second back gate electrode including a second doped region of the semiconductor substrate and being of a second conductivity type.

6 more elements

A memory comprising:

a memory cell that includes:
a silicon substrate;
an insulating layer that overlies the silicon substrate;
a semiconductor layer overlying the insulating layer and including a doped source region, a doped drain region, and an intermediate region between the drain region and the source region;
an insulated front gate electrode overlying the intermediate region;
a first back gate electrode arranged under the insulating layer, opposite the drain region;
and
a second back gate electrode arranged under the insulating layer, opposite the source region;
and
a controller adapted to supply a first bias voltage to the first back gate electrode, a second bias voltage that is different than the first bias voltage to the second back gate electrode, a reference voltage to the source region, a first control signal to the drain region, and a second control signal to the front gate electrode.

7 more elements

A method, comprising:

controlling a memory cell that comprises an insulating layer;
a semiconductor layer that overlies the insulating layer and comprises a doped source region, a doped drain region, and an intermediate region between the drain region and the source region;
an insulated front gate electrode overlying the drain region;
a first back gate electrode arranged under the insulating layer, opposite the drain region;
and a second back gate electrode arranged under the insulating layer, opposite the source, the controlling including:
applying a first bias voltage to the first back gate electrode, a second bias voltage that is different than the first bias voltage to the second back gate electrode, and a reference voltage to the source region;
and
applying a first control signal to the drain region and a second control signal to the front gate electrode.

5 more elements

Dependencies are inferred from the claim text.

Memory cell

Life of this patent

Memory cell

Life of this patent

Abstract

Claims25