Vertical transport transistors with equal gate stack thicknesses

An integrated chip, comprising:

• a first semiconductor device, the first semiconductor device comprising:
• a semiconductor channel;
• a first-type work function layer formed on the semiconductor channel;
• and
• a second-type work function layer formed on the first-type work function layer;
• a second semiconductor device, the second semiconductor device comprising:
• a semiconductor channel;
• a second-type work function layer formed on the semiconductor channel;
• and
• a thickness matching layer formed on the second-type work function layer, the thickness matching layer having a thickness roughly equal to a thickness of the first-type work function layer;
• and
• an inter-device connection that connects the first semiconductor device and the second semiconductor device, comprising portions of the first-type work function layer, the second-type work function layer, and the thickness matching layer.

An integrated chip, comprising:

• a first semiconductor device, comprising:
• a semiconductor channel;
• a first-type work function layer formed on the semiconductor channel;
• a second-type work function layer formed on the first-type work function layer;
• and
• a scavenging layer on the second-type work function layer;
• and
• a second semiconductor device, comprising:
• a semiconductor channel;
• a second-type work function layer formed on the semiconductor channel;
• a scavenging layer on the second-type work function layer;
• and
• a thickness matching layer formed on the scavenging layer, the thickness matching layer having a thickness roughly equal to a thickness of the first-type work function layer.