Memory cells including vertical nanowire transistors

A computer program product, comprising:

• a memory device having stored thereon a machine readable specification of a cell, the specification of the cell including computer readable parameters specifying structural features of a physical implementation of a circuit, the specification being executable by a computer running a placement process to control physical placement of the circuit with other circuits or components or for use by a memory compiler to compile a memory array using the cell, the circuit including:
• an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including a first vertical nanowire transistor on top of and connected in series to a second vertical nanowire transistor.

A circuit, comprising:

• an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including two vertical nanowire transistors in series,
• wherein the set consists of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor.