Fan-out semiconductor package

A semiconductor package comprising:

• a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
• an encapsulant encapsulating at least portions of the semiconductor chip;
• and
• a first connection member disposed on the active surface of the semiconductor chip, and including a first insulating layer disposed on the active surface of the semiconductor chip, a first redistribution layer made of an electrically conductive material and electrically connected to the connection pads through vias in the first insulating layer, a second insulating layer covering the first redistribution layer, and a second redistribution layer electrically connected to the connection pads through at least the first redistribution layer and being in contact with the second insulating layer,
• wherein the first redistribution layer includes a first conductive pattern having a plurality of holes exposing portions of the first insulating layer, respectively, and a second conductive pattern disposed inside one of the plurality of holes,
• the second insulating layer fills the plurality of holes and is in contact with the portions of the first insulating layers exposed by the plurality of holes,
• the second distribution layer includes a third conductive pattern, and
• the third conductive pattern overlaps with the second conductive pattern, when being projected in a direction perpendicular to the active surface.

A semiconductor package comprising:

• a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
• an encapsulant encapsulating at least portions of the semiconductor chip;
• and
• a first connection member disposed on the active surface of the semiconductor chip, and including a first insulating layer disposed on the active surface of the semiconductor chip, a first redistribution layer made of electrically conductive material and electrically connected to the connection pads through vias in the first insulating layer, a second redistribution layer electrically connected to the connection pads through at least the first redistribution layer and disposed on the first redistribution layer, and a second redistribution layer electrically connected to connection pads through at least the first redistribution layer and being in contact second insulating layer,
• wherein the first redistribution layer includes a first conductive continuous pattern having a plurality of holes surrounded by an outer boundary of the first conductive continuous pattern,
• the plurality of holes expose portions of the first insulating layer, respectively,
• the second insulating layer fills the plurality of holes and is in contact with the portions of the first insulating layers exposed by the plurality of holes,
• the second distribution layer includes a second conductive pattern, and
• the second conductive pattern and the first conductive continuous pattern overlap with each other and the second conductive pattern is spaced apart from the plurality of holes, when being projected in a direction perpendicular to the active surface.