Semiconductor package, assembly and module arrangements for measuring gate-to-emitter/source voltage

A semiconductor package, comprising:

• a single controllable power semiconductor die embedded in a molding compound, the power semiconductor die comprising a gate pad, an emitter/source pad and a collector/drain pad;
• a first terminal protruding from the molding compound and electrically connected to the gate pad of the power semiconductor die;
• a second terminal protruding from the molding compound and electrically connected to an additional gate pad of the power semiconductor die;
• a third terminal protruding from the molding compound and electrically connected to the collector/drain pad of the power semiconductor die;
• a fourth terminal protruding from the molding compound and electrically connected to the emitter/source pad of the power semiconductor die;
• and
• a fifth terminal protruding from the molding compound and electrically connected to the emitter/source pad of the power semiconductor die,
• wherein the second terminal and the fourth terminal are configured to carry just a current which is necessary to sense a gate-to-emitter/source voltage of the power semiconductor die,
• wherein the power semiconductor die comprises an integrated gate resistor in series with a gate of a power transistor,
• wherein the additional gate pad is electrically connected to a node between the gate of the power transistor and the integrated gate resistor.