Gate-last semiconductor fabrication with negative-tone resolution enhancement

A method of fabricating a transistor structure, the method comprising:

• forming an active device layer on a semiconductor substrate;
• patterning the active device layer to form a plurality of fins;
• forming a first dielectric layer on at least a portion of an upper surface and sidewalls of the plurality of fins;
• forming a second dielectric layer on at least a portion of an upper surface of the first dielectric layer;
• forming a first plurality of openings through the second dielectric layer and the first dielectric layer, exposing the underlying active device layer forming the plurality of fins;
• forming a plurality of source/drain regions in the active device layer exposed through the respective first plurality of openings;
• forming a plurality of source/drain contacts on an upper surface of each of the plurality of source/drain regions;
• forming a second opening through the second dielectric layer and the first dielectric layer, the second opening exposing the underlying active device layer adjacent to the plurality of source/drain regions;
• depositing a third dielectric layer in at least a portion of the second opening, including on sidewalls of the second opening and sidewalls and an upper surface of the plurality of fins;
• patterning a trench, the trench configured for forming a gate;
• and
• forming the gate on the third dielectric layer using the patterned trench.