Method for forming semiconductor device structure with gate structure

A method for forming a semiconductor device structure, comprising:

• forming an amorphous layer over a substrate, wherein the substrate has a base portion and a fin portion over the base portion, and the amorphous layer covers the fin portion;
• annealing the amorphous layer to crystallize the amorphous layer into a first polycrystalline layer;
• before the annealing of the amorphous layer, forming a second polycrystalline layer over the amorphous layer;
• forming a semiconductor layer over the first polycrystalline layer, wherein a first average grain diameter of the semiconductor layer is less than a second average grain diameter of the first polycrystalline layer;
• and
• removing a first portion of the semiconductor layer and a second portion of the first polycrystalline layer under the first portion, wherein the remaining semiconductor layer and the remaining first polycrystalline layer under the remaining semiconductor layer together form a first gate structure over and across the fin portion.

A method for forming a semiconductor device structure, comprising:

• forming a first semiconductor layer over a substrate, wherein the substrate has a base portion and a fin portion over the base portion, the first semiconductor layer covers the fin portion, and the first semiconductor layer has a first average grain diameter;
• performing an annealing process on the first semiconductor layer, wherein the first average grain diameter is enlarged by the annealing process;
• after the annealing process, forming a second semiconductor layer over the first semiconductor layer, wherein a second average grain diameter of the second semiconductor layer is less than the enlarged first average grain diameter of the first semiconductor layer;
• and
• removing a first portion of the second semiconductor layer and a second portion of the first semiconductor layer under the first portion, wherein the remaining second semiconductor layer and the remaining first semiconductor layer under the remaining second semiconductor layer together form a gate structure over and across the fin portion, wherein the removing of the first portion and the second portion comprises:
• performing a first etching process on the second semiconductor layer to remove the first portion, wherein the second portion of the first semiconductor layer under the first portion is exposed after the first etching process;
• and
• after the first etching process, performing a second etching process on the first semiconductor layer using the second semiconductor layer as an etching mask to remove the second portion.