Field effect transistor stack with tunable work function

A method for fabricating a gate stack of a semiconductor device, the method comprising:

• forming a first dielectric layer over a channel region of the device;
• forming a first nitride layer comprising TaN over the first dielectric layer;
• forming a first gate metal layer comprising NbAlC over the first nitride layer;
• forming a capping layer comprising a nitride over the first gate metal layer;
• removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, the remaining portions of the capping layer and the first gate metal layer and the first nitride layer defining a strong oxygen scavenging niobium aluminum carbonitride stack comprising a first thickness in a n-type field effect transistor (nFET) region of the gate stack;
• depositing a scavenging layer comprising TiAlC or NbAlC on the first nitride layer in the pFET region and on the capping layer in the nFET region such that the scavenging layer and the first nitride layer in the nFET region are formed on opposite ends of the strong oxygen scavenging niobium aluminum carbonitride stack;
• and
• depositing a second nitride layer comprising TiN or TaN on the scavenging layer in both the pFET region and the nFET region such that the second nitride layer, the scavenging layer, and the first nitride layer in the pFET region define a weak oxygen scavenging stack comprising a second thickness and wherein the second nitride layer and the capping layer are of the same composition;
• wherein the first thickness is greater than the second thickness and the second thickness is selected to adjust a threshold voltage in the pFET region and to ensure that the weak oxygen scavenging stack is relatively weaker than the strong oxygen scavenging stack.