Monolithic co-integration of MOSFET and JFET for neuromorphic/cognitive circuit applications

A method of fabricating a monolithic semiconductor structure including a vertical JFET device and a vertical MOSFET device, the method comprising:

• obtaining a first structure including:
• a heavily doped source/drain layer including first and second bottom source/drain regions,
• an isolation region electrically isolating the first bottom source/drain region from the second bottom source/drain region,
• a bottom electrically insulating spacer above the heavily doped source/drain layer,
• a top electrically insulating spacer above and parallel to the bottom electrically insulating spacer, and
• a sacrificial layer between the bottom and top electrically insulating spacers;
• forming first and second vertical trenches, each of the first and second vertical trenches extending through the bottom and top electrically insulating spacers and the sacrificial layer;
• epitaxially growing first and second semiconductor channels and first and second channel material extensions, the first and second semiconductor channels being grown within the first and second trenches such that the first semiconductor channel is doped and adjoins the first bottom source/drain region, the second semiconductor channel adjoins the second bottom source/drain region, and the first and second channel material extensions are integral, respectively, with the first and second semiconductor channels and extend above the top electrically insulating spacer;
• epitaxially growing heavily doped first and second top source/drain regions, respectively, on the first and second channel material extensions;
• removing a first portion of the sacrificial layer above the first bottom source/drain region;
• epitaxially growing a heavily doped semiconductor gate on the first semiconductor channel and between the bottom and top electrically insulating spacers, the heavily doped semiconductor gate and the first semiconductor channel having opposite conductivity types;
• removing a second portion of the sacrificial layer above the second bottom source/drain region;
• forming a gate dielectric layer on the second semiconductor channel between the bottom and top electrically insulating spacers, and
• forming a metal gate over the gate dielectric layer.